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Last updated: June 21, 2019

Hello W orld using M icro B laze Tutor: Tuan L e Tutee: Tiago Campos Student ID: M00596777 PDE3411 – System -On -a-Chip Design Date: 0 7/11/20181 | P a g e Contents Introduction ….

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3 Hello world project ….

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……………………. ………………………….. ………………………….. .. 17 Conclusion ………………………….. ………………………….. ………………………….. ………………………….. …………. 25 References ………………………….. ………………………….. ………………………….. ………………………….. ………… 262 | P a g e INTRODUCTION MicroBlaze is a software microprocessor core designed by Xilinx for FPGA’s ( field -programmable gate arrays ). Th e MicroBlaze is a reduced instruction set computer (RISC) optimized for implementation on Xilinx FPGA’s (Xilinx. com, 2018) . Because MicroBlaze is a software micro processor , it is entirely implemented in the general -purpose memory and logic fabric of Xilinx FPGAs (ARTICLES et al., 2018) . This soft -core processor is the topic of this report and it is going to be explained what MicroBlaze is and how to serial print a Hello World using the MicroBlaze processor by using Vivado and the Software Development Kit (SDK) .3 | P a g e BACKGROUND RESEARCH MicroBlaz e is a soft core processor with 32 -bit RISC Harvard architecture with a rich instruction set optimized for embedded applications. The MicroBlaze offers to its users’ complete flexibility to select the combination of peripheral, memory and interface features that will give you the exact system you need at the lowest cost possible on a single FPGA (Xilinx.com, 2018) . Some of the advantages of using MicroBlaze versus typical microprocessors are customization, obsolescence mitigation, component cost reduction, and hardware acceleration (Xilinx.com, 2018) . Since MicroBlaze is an Eclipsed -based Xilinx Software Development Kit any system designer or programmer with no prior FPGA experience will be able to program it as it uses more common programming languages such as C or C++. MicroBlaze meets the requirements to operate several demanding applications such as Medical , Aircrafts , Industrial, etc . Another great advantage of using MicroBlaze is the capability to operate as a real -time processor (RTOS), which means that it can run continuously (Xilinx.com, 2018) . It is also highly configurable , it allows the user to select the specific set of features it desires making it a great tool for implementing with detail the user design. VHSIC (Very High Speed Integrated Circuit) Hardware Description Language ) or VHDL is the programming language used for programming the hardware (Vivado) and for programming the software (SDK) the language used was C but it could also have been used C++. The MicroBlaze processor instructions executions are pipelined and d epending on the design requirements, the user can select a 3-stage pipeline architecture (Area Optimized configuration) or a 5-stage pipeline architectu re (Performance Optimized configuration) (Xilinx.com, 2018).4 | P a g e It is also important to mention the IP core AXI. AXI stands for Advanced eXtensible Interface which is part of ARM AMBA, a family of micro controller buses (Xilinx.com, 2018) . In this project it is used the LogiCORE IP AXI Universal Asynchronous Receiver Transmitter (UART) lite interface which connects t o the Advanced Microcontroller Bus Architecture (AMBA) AXI and provides controller interface for asynchronous serial data transfer (Xilinx.com, 2018) . AXI Uartlite is one of the most important IP cores in the project that follows. Figure 1 – MicroBlaze Core Block Diagram (Slideplayer.com, 2018) .5 | P a g e H ELLO W ORLD PROJECT The Hello World is a n example code found in many programmable devices , it is used as a beginner way of learning the new programming language . Before proceeding it is necessary to make sure the following software is installed : ? Vivado 2015 .01 or later (Vivado 2018.2 was the version used in this tutorial ). ? Xilinx S oftware Deve lopment Kit (Xilinx SDK 2018.02 was the version used in this tutorial) . The following hardware is also required : ? Nexys4 DDR FPGA board . ? USB cable to connect computer and Nexys4. First step is checking if the software version supports the board being used. If it is not the case an update would be required. For reference pur poses , the following link provides the content to download and instructions to add the boards to the Vivado software. To download the Nexys4 DDR FPGA board and follow the instructions access the following link: https://reference.digilentinc.com/reference/software/vivado/board -files?redirect=1 Figure 2 – Nexys4 DDR download and instructions webpage .6 | P a g e Hardware (Vivado) Started by l aunching the Vivado software and creat ing a new project by going to File ;Project;New . Then the file was named (e.g. HelloWorld ) and the project location chosen . Note that t he file name cannot have spaces in them as it cause s issues with Vivado. Figure 3 – Creating a Vivado project.7 | P a g e On the type of project RTL (Register -transfer level) Project option was selected . On the purpose of making the explanation as clear as possible the “Do not specify sources at this time” box was checked . If the box had been left unselected the sources had to be spe cified . Figure 4 – Choosing the project type.8 | P a g e The next step was to select the correspondent part (XC7A100T -CSG324) and board (Nexys 4 DDR) and double check on the project summary window if everything was correct. Figure 5 – Project summary.9 | P a g e On ce on Vivado , the language of the new project was Verilog by default and a change to VHDL was needed. For doing this went to target language on project summary and double click ed to change it to VHDL . Afterwards, a Block Design was created, and a name was chosen for the Design. Figure 6 – Vivado overview. Figure 7 – Creating a Block Design.10 | P a g e When a block design is created it is necessary to program in VHDL to create a design . However, it is not practical to do so nowadays as the complexity of the projects requires a lot of different designs. For this reason, IP was created and with it became possible to access to pr eviously ma de designs making it easier to anyone to program their own block design. On the Diagram pane l the “Add an IP” option was selected and searched for MicroBlaze, AXI Uartlite and the Clock ing Wizard. After a dding the Clocking Wizard, the clock reset type was changed from active high to active low by double clicking on the Clocking Wizard diagram. Figure 8 – Changing Clocking Wizard from Active High to Active Low.11 | P a g e Once all IPs are in place it is necessary to connect them. For doing that “Run Block Automation ” was selected ( all the options were ticked) and the sam e was done with “Run Con nection Automation ” option . Figure 9 – Connecting the IP with Block and Connection automation. After everything is connected it is advisable to “V alidate ” the design to check for errors, and for easier understanding of the design click also on “Regenerate Layout”.12 | P a g e On figure 10 is shown how the Block D iagram should look after all the given steps so far. Figure 10 – Block Diagram complete.13 | P a g e The next step was to create a Top -Level file by creating a n HDL Wrappe r. This can be done by double clicking on the vhd file in the sources tab and selecting the “Create HDL Wrapper” option. Figure 11 – Creating the Top -Level file / HDL Wrapper.14 | P a g e Once the HDL Wrapper was done the next step was to click on “Generate Bitstream “, found on the flow navigator . A couple of minutes were needed to generate the bitstream . Once completed a window opened and ” Open implemented design” option was selected. Figure 12 – Bitstream generation.15 | P a g e After t he Bitstream wa s generated successfully the next step wa s to Export the Hardware and L aunch the Xilinx S oftware Development Kit (SDK) by select ing File;Export;Export Hardware . In the window that follows tick the box with the option “Include Bitstream”. Figure 13 – Export hardware.16 | P a g e That conclude d the Hardware creation on Vivado and it was needed to select the “Launch SDK” option in order to import the hardware data prepared on Vivado to the Xilinx SDK . Figure 14 – Launching Xilinx SDK.17 | P a g e Software (SDK) The Xilinx So ftware Development Kit (SDK) is a software that allows the creation of embedded applications of any Xilinx’s microprocessors. It is used for multi -processor design, debug and performance analysis (Xilinx.com, 2018) . On the Xilinx SDK it was created a new application project by going to F ile>New>Application Project . Figure 15 – Creating new application project on the Xilinx SDK. When the Application Project is created , other modules are also created such as the Board Support Package (BSP) which provides a layer of abstraction from the physical board. With the BSP different hardware such as buttons, LEDs, UART and other hardware peripherals can be targeted with the same code (Nordic DevZone, 2 018) .18 | P a g e In this particular project is present the Hello World C code , the Board Support Package and the HDL Wrapper. On the application project overview window, it can be found the options to create a Board Support Package (BSP) , choose the programming language between C and C++, choose the hardware platform and the processor and the OS platform. For the purpose of this example was needed to change the option s as shown in Figure 1 6. Figure 16 – Creating an application project on SDK.19 | P a g e Figure 17 – Selecting the Hello World template.20 | P a g e At this stage the Nexys4 FPGA board had to be connected to the computer via USB. From the project explorer menu, the source file was opened. Then by going to the terminal and clicking on the (+) ic on a serial port had to be chosen. Subsequently t he baud was changed to 9600 in order to match the baud that it was previously chosen on Vivado. Figure 18 – Finding the terminal and connecting to a serial port. Figure 19 – Selecting the Baud and port.21 | P a g e Once the Baud and Port were configurated, the option “Program FPGA” on the Xilinx tab was selected. Finishing this step by clicking “Program ” on the following window. Figure 20 – Program the FPGA.22 | P a g e This option of Program FPG A entitl es specifying the Bitstream and BMM files . After th e FPGA ha d been programmed tab “R un ” was selected and the option “Ru n” from the drop -in menu c hosen . The window that followed requested a way to run the software and ” Launch on Hardware (GDB) ” option was selected .23 | P a g e Finally, the message Hello World appear ed on the terminal. Figure 21 – Running the code.24 | P a g e On this project it was used the built in SDK terminal but there is other third -party software available such as Putty . Putty is a free open -source software that supports sever al network protocols and t hat can be used as terminal emulator , serial console , etc . Figure 22 – Hello World on the terminal.25 | P a g e CONCLUSION In this report it was taught what is a MicroBlaze, some of its characteristics and some of the advantages of using this softcore processor. It was also mentioned the several software used on the Hello World project and what the Hello World example is. It was taught how to serial print a message onto the SDK terminal using th e MicroBlaze software processor and programming it with Vivado and the Xilinx Software Development Kit . It was shown that u sing the MicroBlaze it is easier to program since is written in C programming language opposed to VHDL or Verilog as most FPGA’s are normally programmed. As a Xilinx board, the Nexys4 DDR board was the board chosen for the Hello World project.26 | P a g e REFERENCES ? ARTICLES, T., PRODUCTS, N., ELECTRONICS, G., PROJECTS, C., MICRO, E., Lectures, V., Webinars, I., Training, I., Search, P., DB, T., Tool, B. and Designs, R. (2018). Utilizing Xilinx’s MicroBlaze in FPGA Design . online Allaboutcircuits.com. Available at: https://www.allaboutcircuits.com/industry -articles/utilizing -xilinx -microblaze -in-fpga – design/ Accessed 31 Oct. 2018. ? Xilinx.com. (2018). MicroBlaze Soft Processor Core . online Available at: https://www.xilinx.com/products/design -tools/microblaze.html Accessed 31 Oct. 2018. ? Xilinx.com. (2018). MicroBlaze . online Available at: https://www.xilinx.com/products/intellectual -property/microblazecore.html#overview Accessed 31 Oct. 2018. ? Xilinx.com. (2018). online Available at: https://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf Accessed 1 Nov. 2018. ? Nordic DevZone. (2018). Board support package (BSP) . online Available at: https://devzone.nordicsemi.com/tutorials/b/software -development -kit/posts/board – sup port -package -bsp Accessed 1 Nov. 2018. ? Xilinx.com. (2018). online Available at: https://www.xilinx.com/support/documentation/white_papers/wp469 -microblaze -for -cost – sensitive -apps.pdf Accessed 1 Nov. 2018. ? Slideplayer.com. (2018). online Available a t: http://slideplayer.com/slide/7032837/24/images/52/MicroBlaze – based+Embedded+Design.jpg Accessed 2 Nov. 2018. ? Xilinx.com. (2018). Xilinx Software Development Kit (XSDK) . online Available at: https://www.xilinx.com/products/design -tools/embedded -software/sdk.html Accessed 5 Nov. 2018. ? Xilinx.com. (2018). online Available at: https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf Accessed 5 Nov. 2018. ? Xilinx.com. (2018). AXI UART Lite . online Available at: https://www.xilinx.com/products/intellectual -property/axi_uartlite.html Accessed 5 Nov. 2018.

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